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100331 Low Power Triple D-Type Flip-Flop
February 1990 Revised August 2000
100331 Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 k pull-down resistors.
Features
s 35% power reduction of the 100131 s 2000V ESD protection s Pin/function compatible with 100131 s Voltage compensated operating range = -4.2V to -5.7V s Available to industrial grade temperature range
Ordering Code:
Order Number 100331SC 100331PC 100331QC 100331QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40C to +85C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names CP0-CP2 CPC D0-D2 CD0-CD2 SDn MR MS Q0-Q2 Q0-Q2 Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs 28-Pin PLCC
(c) 2000 Fairchild Semiconductor Corporation
DS010262
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100331
Truth Tables
Synchronous Operation (Each Flip-Flop) Inputs Dn L H L H X X X CPn Outputs MS SDn L L L L L L L MR CDn L L L L L L L Qn(t + 1) L H L H Qn(t) Qn(t) Qn(t) Dn X X X CPn X X X Asynchronous Operation (Each Flip-Flop) Inputs CPC X X X MS SDn H L H MR CDn L H H Outputs Qn(t + 1) H L U

L L L H X
CPC L

L L X H
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care U = Undefined t = Time before CP Positive Transition t + 1 = Time after CP Positive Transition = LOW-to-HIGH Transition
Logic Diagram
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Absolute Maximum Ratings(Note 1)
Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Pin Potential to Ground Pin (VEE) Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2)
-65C to +150C +150C -7.0V to +0.5V
VEE to +0.5V
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0C to +85C
-40C to +85C -5.7V to -4.2V
-50 mA 2000V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version DC Electrical Characteristics (Note 3)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0C to +85C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current -122 -1165 -1830 0.5 240 -65 Min -1025 -1830 -1035 -1610 -870 -1475 Typ -955 -1705 Max -870 -1620 Units mV mV mV mV mV mV A A mA VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs OPEN Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V
Note 3: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100331
Commercial Version (Continued) DIP AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Transition Time 20% to 80%, 80% to 20% Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) tH tPW(H) Hold Time Dn Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3, 4 0.40 1.30 2.30 0.5 0.40 1.30 2.30 0.5 0.40 1.30 2.30 0.7 ns ns Figure 4 Figure 5 Propagation Delay MS, MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output TC = 0C Min 375 0.75 0.75 0.70 0.70 1.10 1.10 0.35 2.00 2.00 1.70 2.00 2.60 2.80 1.30 Max TC = +25C Min 375 0.75 0.75 0.70 0.70 1.10 1.10 0.35 2.00 2.00 1.70 2.00 2.60 2.80 1.30 Max TC = +85C Min 375 0.75 0.75 0.70 0.70 1.10 1.10 0.35 2.00 2.00 1.80 ns 2.00 2.60 ns 2.80 1.30 ns CPn, CPC = H Figures 1, 3, 4 Figure 5 CPn, CPC = H Figures 1, 4 CPn, CPC = L Max MHz ns Figures 1, 3 ns CPn, CPC = L Figures 2, 3 Units Conditions
SOIC and PLCC AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Transition Time 20% to 80%, 80% to 20% Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) tH tPW(H) Hold Time Dn Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3, 4 0.30 1.20 2.20 0.5 0.30 1.20 2.20 0.5 0.30 1.20 2.20 0.7 ns ns Propagation Delay MS, MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output TC = 0C Min 400 0.75 0.75 0.70 0.80 1.10 1.10 0.35 1.80 1.80 1.50 1.80 2.40 2.60 1.10 Max TC = +25C Min 400 0.75 0.75 0.70 0.70 1.10 1.10 0.35 1.80 1.80 1.50 1.80 2.40 2.60 1.10 Max TC = +85C Min 400 0.75 0.75 0.70 0.70 1.10 1.10 0.35 1.80 1.80 1.60 ns 1.80 2.40 2.60 1.10 ns CPn, CPC = H Figures 1, 4 ns CPn, CPC = L CPn, CPC = H Figures 1, 3, 4 Figure 5 Figure 4 Figure 5 Max MHz ns Figures 1, 3 ns CPn, CPC =L Figures 2, 3 Units Conditions
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Commercial Version
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tOSHL Propagation Delay MS, MR to Output Parameter Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output
(Continued)
TC = 0C Min 0.75 0.70 0.70 0.80 1.10 1.20 Max 1.40 1.40 1.50 1.70 2.00 2.10 TC = +25C Min 0.75 0.75 0.70 0.80 1.10 1.20 Max 1.40 1.40 1.50 1.70 2.00 2.10 TC = +85C Min 0.80 0.80 0.80 0.80 1.20 1.30 Max 1.50 1.50 1.60 ns 1.80 2.10 ns 2.20 ns Figures 1, 3 PLCC Only ns CPn, CPC =L PLCC Only CPn, CPC = H PLCC Only CPn, CPC = L PLCC Only CPn, CPC = H PLCC Only PLCC Only 100 100 100 ps (Note 4) PLCC Only 235 235 235 ps (Note 4) PLCC Only 120 120 120 ps (Note 4) PLCC Only 275 275 275 ps ps 125 125 125 ps 265 265 265 (Note 4) PLCC Only (Note 4) PLCC Only (Note 4) PLCC Only 90 90 90 ps (Note 4) PLCC Only 90 90 90 ps (Note 4) Figures 1, 4
Units
Conditions
Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path
tOSHL
Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path
tOSLH
Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path
tOSLH
Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path
tOST
Maximum Skew Opposite Edge Output-to-Output Variation Common Clock to Output Path
tOST
Maximum Skew Opposite Edge Output-to-Output Variation CPn to Output Path
tPS
Maximum Skew Pin (Signal) Transition Variation Common Clock to Output Path
tPS
Maximum Skew Pin (Signal) Transition Variation CPn to Output Path
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design.
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100331
Industrial Version PLCC DC Electrical Characteristics (Note 5)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -40C to +85C TC = -40C TC = 0C to +85C Symbol Parameter Min Max Min Max VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current -122 -1170 -1830 0.5 300 -60 -122 -1085 -1830 -1095 -1565 -870 -1480 -1165 -1830 0.5 240 -65 -870 -1575 -1025 -1830 -1035 -1610 -870 1475 -870 -1620 Units mV mV mV mV mV mV A A mA VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V
Note 5: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
PLCC AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND TC = -40C Symbol Parameter Min Max fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Transition Time 20% to 80%, 80% to 20% Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) tH tPW(H) Hold Time Dn Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS 2.00 2.00 2.00 ns Figures 3, 4 1.00 1.50 2.50 0.7 0.30 1.20 2.20 0.5 0.30 1.20 2.20 0.7 ns ns Propagation Delay MS, MR to Output Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output 375 0.75 0.70 0.60 0.70 1.10 1.10 0.20 1.80 1.80 1.50 1.80 2.40 2.60 1.40 TC = +25C Min 400 0.75 0.75 0.70 0.70 1.10 1.10 0.35 1.80 1.80 1.50 1.80 2.40 2.60 1.10 Max TC = +85C Min 400 0.75 0.75 0.70 0.70 1.10 1.10 0.35 1.80 1.80 1.60 ns 1.80 2.40 ns 2.60 1.10 ns CPn, CPC = H Figures 1, 3, 4 Figure 5 Figure 4 Figure 5 CPn, CPC = H Figures 1, 4 CPn, CPC = L Max Units MHz ns ns CPn, CPC = L Conditions Figures 2, 3 Figures 1, 3
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Test Circuits
FIGURE 1. AC Test Circuit
Notes: VCC, VCCA = +2V, VEE = -2.5V L1 and L2 = Equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 F from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF
FIGURE 2. Toggle Frequency Test Circuit
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Switching Waveforms
FIGURE 3. Propagation Delay (Clock) and Transition Times
FIGURE 4. Propagation Delay (Resets)
FIGURE 5. Data Setup and Hold Time
Note: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E
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100331 Low Power Triple D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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